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STB4395
CT2 RECEIVER/TRANSMITTER
. . . . . . . . . . . .
ADVANCE DATA
FULLY INTEGRATED DOUBLE SUPERHETERODYNE RECEIVER OPERATION FROM 800MHz TO 1000MHz RECEIVER OUTPUT AS BITSTREAM FULLY INTEGRATED TRANSMITTER TRANSMITTER INPUT I/Q/REFIQ OR I/I, Q/Q INTEGRATED POWER AMPLIFIER CT2 PA SWITCH-ON PROFILE INTEGRATED VCO's INTEGRATED SYNTHESIZERS INTEGRATED CHANNEL SELECT LOGIC ON CHIP INTEGRATED VOLTAGE REGULATION SUPPLY VOLTAGES FROM 3.0V TO 5.5V
DESCRIPTION The STB4395(A) is a fully integrated receivertransmitter designed for CT2 applications, and incorporates all the VCO's, synthesizers, PLLs, and channel select logic, to make a fully functional "single chip" radio. The receiver is of the double superhet architecture and operates from an aerial input (via a SAW filter) to bitstream output to CT2 format, whilst the transmitter operates from I/Q inputs to +13dBm at the final frequency. A single (external) frequency reference is all that is required to give full coverage over the range of 800 to 1000MHz.The on-off slope of the Transmit PAis governed internally to give the required switch-on ramp, whilst the output can be swiched from low to high power by means of an external digital control signal. The channelselect is controlled from a digital serial input, and allows continuous channel control from 800 to 1000MHz. T h e S TB 4 3 9 5 e x is t s in t wo v ersio n s: the STB4395, which has I/I, Q/Q transmit data input/outputs, is designed to operate with the SGS-THOMSON baseband companion part, the ST5095. The STB4395A has a 3 wire I/Q interface and is compatible with commercially available I/Q transmit data baseband IC's.
April 1996
TQFP64 (Plastic Package) ORDER CODE : STB4395 or STB4395A
1/16
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
STB4395 CONTENT
1 1.1 1.2 1.3 1.4 1.5 2 3 3.1 3.2 3.3 4 5 5.1 5.2 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.11.1 8.11.2 9 9.1 9.1.1 9.1.2 9.2 9.2.1 9.2.2 10
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Page
3 4 5 5 6 6 7 8 8 8 8 8 9 9 9 9 9 9 9 10 10 11 11 11 11 12 13 13 13 13 13 14 14 14 14 14 15 15 15 15 15 15 15 16 ................ ... ... .... . .. ... ................ .. .. . .. . .. . . . . . . .. .. . .. . .. .. .. . .
PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANALOG AND FILTER PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL, SIGNAL AND CONTROL PINS. . . . . . . . . . . . . . . . . . . . POWER SUPPLY PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMITTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHANNEL SELECT CONTROL LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUPPLIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GROUND PLANE CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TURN ON-OFF TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHANNEL SELECT TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSCEIVER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER-INPUT SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMITTER OUTPUT SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYNTHESIZER/MODULATOR/CHANNEL SELECT LOOP . . . . . . . . . . . . . . . . . . . . . . Synthesizer phase noise and spurious . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel select loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSTEM CLOCK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER -RF INPUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL INPUT BUFFERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL OUTPUT BUFFERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER- FSH TRI STATE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVER- RSSI OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER DOWN BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMITTER - DATA INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STB4395A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STB4395 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TYPICAL DC CONNECTION SCHEMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPLICATION CIRCUIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STB4395
1 - PIN DESCRIPTION 1.1 - Pin Connections
STB4395
ADJPWR NTXFLT NSAWI SHAPE TXFLT VPRF2 VPRF1 VNPA VNRF 48 47 46 45 44 43 42 VRRF SAWI VND VRD VPD NRF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NPRGEN P RGCLK P RGD NTXEN LOCK I NI NQ Q EN VNOSC S YNCLK VRO VCOO NVCOO FLTRO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VNIF SAWO NSAWO VPIF NIF2O IF2O DEC IF2I NIF2I NDEC VRIF RSSI VRI VCOI NVCOI FLTRI
TQFP64
(from above )
RF
41 40 39 38 37 36 35 34 33
STB4395A
ADJPWR NTXFLT NSAWI SHAPE TXFLT VPRF2 VPRF1 VNPA VNRF VRRF SAWI VND VRD VPD NRF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NPRGEN P RGCLK P RGD NTXEN LOCK I REFIQ Q FN EN VNOSC S YNCLK VRO VCOO NVCOO FLTRO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 VNIF SAWO NSAWO VPIF NIF2O IF2O DEC IF2I NIF2I NDEC VRIF RSSI VRI VCOI NVCOI FLTRI
TQFP64
(from above )
RF
41 40 39 38 37 36 35 34 33
3/16
4395-02.EPS
NVCOS
FLTRS
VCOS
DISCI
VPO
VRS
DISCO
BRF3
BRF1
BRF2
SLTC
FSH
VPS1
VPS2
VPI
DO
4395-01.EPS
NVCOS
FLTRS
VCOS
DISCI
VPO
VRS
DISCO
BRF3
BRF1
BRF2
SLTC
FSH
VPS1
VPS2
VPI
DO
STB4395
1 - PIN DESCRIPTION (continued) 1.2 - Pin List
Pin 1 2 3 4 5 6 7 8 9 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 4/16 Name NPRGEN PRGCLK PRGD NTXEN LOCK I NI NQ Q REFIQ Q FN EN VNOSC SYNCLK VRO VCOO NVCOO FLTRO VPO DO SLTC FSH FLTRS VRS VPS1 NVCOS VCOS VPS2 BRF3 BRF1 DISCI DISCO BRF2 VPI FLTRI NVCOI VCOI VRI RSSI VRIF NDEC NIF2I IF2I DEC IF2O NIF2O VPIF Description Serial Data Enable Serial Data Clock Serial Data Input Receive-Transmit Switch VCO Lock Detect-all 3 PLL I - Transmit Quadrature Input I - Transmit Quadrature Input Q-Transmit Quadrature Input Q-Transmit Quadrature Input IQ Reference Quadrature Transmit Input Q-Transmit Quadrature Input Forces Data Slicer Reference Time Constant To fast Power Down all functions except buffer Negative Power Supply all VCO 's Synthesizer Clock Input PSU Regulated Negative Input for TX IF oscillator and pump circuit TX oscillator tank circuit TX Oscillator Tank Circuit Loop Filter for TX PLL Positive Battery Supply for TX oscillator Receive Data Output Slicer Time Constant Capacitor Data Slicer Time Constant Setting Loop Filter for channel PLL Regulated Negative Supply for channel oscillator and pump circuit Positive Battery Input for channel oscillator and pump circuit Channel Oscillator Tank Input Channel Oscillator Tank Input Positive Battery Supply Input for channel oscillator and pump circuit Bit Rate Filter3 Bit Rate Filter1 FM Discriminator Tank Circuit FM Discriminator Tank Circuit Bit Rate Filter 2 Positive Battery Supply for RXoscillator and pump circuit Loop Filter for RX oscillator RX Oscillator Tank Circuit RX Oscillator Tank Circuit Regulated Negative Supply for RX oscillator and pump circuit RSSI OUTPUT Regulated Negative Supply Output for RX sections RX IF2 Decoupling RX IF2 Filter Input RX IF2 Filter Input RX IF2 Decoupling RX IF2 Filter Output RX IF2 Filter Output Positive Battery Supply Input for RX sections Ext. Connection and Suppl. Information
STB4395 only STB4395 only STB4395 only STB4395A only STB4395A only STB4395A only
f = 14.4MHz A.C. coupled
C= 33nF
650 to 850MHz 650 to 850MHz
STB4395
1 - PIN DESCRIPTION (continued) 1.2 - Pin List (continued)
Pin 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name NSAWO SAWO VNIF VNRF SAWI NSAWI VRRF VNPA VPRF1 NRF RF VPRF2 ADJPWR SHAPE TXFLT NTXFLT VPD VRD VND Description RX First IF Amplifier Input RX First IF Amplifier Input Negative Battery Supply Input for RX sections Negative Battery Supply Input for RF front end RX First Mixer Output RX First Mixer Output Regulated Negative Supply for RF front end Negative Supply for power amplifier Positive Battery Supply for RF front end Input LNA/Output PA Input LNA/Ouput PA Positive Battery Supply for RF front end Transmit Power Adjust Time Constant for PA on-off ramp Bandpass Filter for TX RF Bandpass Filter for TX RF Positive Battery Supply for digital circuitry Regulated Negative Supply for digital circuitry Negative Battery Supply for digital circuitry Ext. Connection and Suppl. Information
R = 8.5k to VRRF C = 560pF
1.3 - Analog and Filter Pins
Pin 58 28 31 27 42, 39 29 30 33 16 21 6, 7 40, 41 43, 44 8, 9 7 56, 55 37 50, 51 47, 46 59 19 12 60, 61 35, 34 14, 15 25, 24 Symbol ADJPWR BRF1 BRF2 BRF3 DEC, NDEC DISCI DISCO FLTRI FLTRO FLTRS I, NI(1) IF2I, NIF2I IF2O, NIF2O Q, NQ(1) REFIQ RF, NRF RSSI SAWI, NSAWI SAWO, NSAWO SHAPE SLTC SYNCLK TXFLT/ NTXFLT VCOI, NVCOI VCOO, NVCOO VCOS, NVCOS Description Transmitter Output Power Adjust Bit Rate Filter1 Bit Rate Filter 2 Bit Rate Filter 3 RX IF2 Amplifier Decoupling FM Discriminator Tank Circuit FM Discriminator Tank Circuit Loop Filter for RX PLL Loop Filter for TX PLL Loop Filter for Channel PLL Transmit Quadrature Inputs ((1)STB4395 only) Inputs from 2nd IF Filter Outputs to 2nd IF Filter Q-Transmit Quadrature Input ((1)STB4395 only) IQ Reference Quadrature Transmit Input (STB4395A only) Input RX LNA/Ouput TX PA Received Signal Strength Indicator Output First Mixer Output First IF Amplifier Input Time Constant for PA on-off Ramp Slicer Time Constant Capacitor Synthesizer Clock Input 14.4MHz Bandpass Filter for TX RF Tank Circuit for 152.1MHz RX Oscillator Tank Circuit for 300.8MHz TX Oscillator Tank Circuit for 650 to 850MHz Channel Oscillator 5/16
STB4395
1 - PIN DESCRIPTION (continued) 1.4- Digital, Signal and Control Pins
Pin 18 20 9 5 3 Symbol DO FSH FN LOCK PRGD Description Receive Data Output Data Slicer Time Constant Setting (Fast/Slow/Hold) Forces Data Slicer Reference Time Constant to fast (STB4395A only) VCO lock detect-all 3 PLL Serial Synthesizer Data Input, 16 bits word High: slow, tri-state: fast, low: hold DO goes high on hold (see next table) low: fast (overides FSH) high: fast, slow or hold (set by FSH) high for LOCK (all three PLL's) high for logic 1. Input sequence: LO, D14, D13,...,D0. D14 is the MSB. LO: logic 1 is low transmit power. low to enable PRGD buffer held high when no clocking, clocks in data on positive edge high for power up, low for standby high for receive, low for transmit Polarity
1 2 10 4
NPRGEN PRGCLK EN NTXEN
Serial Synthesizer Data Enable Serial Data Clock Power Down all functions except Enable Buffer Receive-Transmit Switch
The time constant of the data slicer is set through the pins FSH and FN for the STB4395A and through FSH only for the STB4395(FN internally connected to High), as listed in the following table :
PIN High FSH TriState Low FN High Slow, DO active Fast, DO active Hold, DO high Low Fast, DO active Fast, DO active Fast, DO high
1.5 - Power Supply Pins
Pin 64 48 11 49 53 62 32 45 17 54, 57 23, 26 63 36 38 13 52 22 Symbol VND VNIF VNOSC VNRF VNPA VPD VPI VPIF VPO VPRF1 / VPRF2 VPS1/ VPS2 VRD VRI VRIF VRO VRRF VRS Description Negative supply for digital regulators, digital input and output buffers Negative supply for IF regulators, data output buffer Negative supply for the oscillator regulators + substrate Negative supply RF regulators, quadrature input buffers Negative supply for PA Positive supply for digital circuitry Positive supply for receive oscillator + charge pump Positive supply for RX IF + baseband sections Positive supply for transmit oscillator + charge pump Positive supplies for RF front end Positive supplies for ch. select oscillator + charge pump Regulated negative supply for digital circuitry Regulated negative supply for receive oscillator + charge pump Regulated negative supply for RX IF + baseband sections Regulated negative supply for transmit oscillator + charge pump Regulated negative supply for RF front end Regulated negative supply ch. select oscillator + charge pump
6/16
STB4395
2 - BLOCK DIAGRAM Figure 1
RF S AW 866.05MHz LC IF S AW
NTXFLT
NSAWI
TXFLT
SAWI
NRF
RF
150.4MHz
61
60
56
55
51
50
LNA PA NTXEN 4 P A/LNA CONTROL 1 1 1 1 CONTROL DECODER IQ Modu lator I IQ Inp ut Da ta Q /2 Tx Mixe r
1s t Mixe r
NP RGEN S yn the s ize r P RGCLK Contro l P RGD
1 2 3
47 46 15 SYNTHESIZER 2nd Mixe r 44 43 41 40
SAWO NSAWO NIF2O IF2O IF2I NIF2I 1.7MHz LC
S YNCLK 14.4MHz
12
REFERENCE DIVIDERS
2nd IF Amplifier
Tx DIVIDER
Rx DIVIDER
VCOO VCO TANK NVCOO
P HASE DETE CTOR 14 15 Tra ns mit VCO 300.8MHz
PHASE DETE CTOR
P HASE DETECTOR
37 35
RS S I VCOI NVCOI VCO TANK
CHARGE P UMP
CHARGE P UMP
CHARGE P UMP
34
PLL FILTER
FLTRO
16 FM Modulator Cha nne l VCO 71 6.45 MHz DATA S LICER Re ce ive VCO 152.1MHz
33
FLTRI
P LL FILTER
STB439 5
24 NVCOS 25 VCOS 21 DO FLTRS 18 19 SLTC FSH 20 27 BRF3 28 BRF1 31 BRF2 29 DISCI 30 DISCO
50kHz Bit Ra te Filter
7/16
4395-03.EPS
VCO TANK
P LL FILTER
Da ta Out
DEMOD. TANK
STB4395
3 - FUNCTIONAL DESCRIPTION Figure 1 is a simplified block diagram of the circuit. It shows the key on-chip and off-chip functional blocks and signal paths. For illustration purposes frequencies have been added representing the situation when receiving or transmitting a particular CT2 channel. 3.1 - Receiver The receive signal enters the STB4395 via an input SAW filter (866 MHZ for CT2 in Europe). The RF filter changes the input signal from a single ended to a balanced signal, after which the signal passes through the LNA, first mixer, and mixer buffer. The mixer is driven by the channel VCO, which is in turn controlled by the synthesizer. The signal path continues via the first IF SAW (150.4MHz), IF amplifier to the second mixer. The second mixer stage mixes down to 1.7MHz, and via an external LC IF filter, is passed to the second IF amplifier, where the main system gain takes place. The RSSI output is available from this point.The signal is then demodulated and sliced into a data stream which is the binary digital output available to the base band chip. The channel selection is provided by the two external filters: the first IF SAW and a second IF 2-pole LC filter. 3.2 - Transmitter The chip accepts 72Kbits/s data in an I/Q format. The I/Q inputs pass via the I/Q modulator to the TX mixer. The TX mixer is driven by the same channel VCO as the receive first mixer. 4 - ABSOLUTE MAXIMUM RATINGS
Symbol VP-VN VP - VIN VP - VIN VIN - VN VP- VOUT VN - VOUT VRFO Tstg Toper Power Supply Voltage Voltages on Input (except SYNCLK) Voltage on Input (SYNCLK) Voltages on Input Voltages on Output Voltages on Output Voltage Out of RF or NRF in TX Storage Temperature Operating Temperature Parameter Value 7.0 5.9 3.0 7.0 7.0 7.0 3.5 125 40 Unit V V V V V V VPP
o o
The on-off ramp of the transmit PA.is controlled via an external capacitor to give minimum spurious responses when switching on and off. The PA output power can be switched from full power to -3dBm by the channel select control signal (bit LO of the 16bits serial word PRGD, see table, paragraph 1.4). 3.3 - Channel Select Control Logic All channel phase locked loops and oscillators are included on chip. The channel control synthesizer is controlled externally via a 3 wire interface. The Reference clock input of 14.4 MHz is divided using preset counters to set the phase detector /charge pump loops for the synthesizer/channel select VCO, the second receiver VCO, and the I/Q transmit VCO. The phase detector inputs for the fixed frequency VCO's arevia pre set dividers also. The channel select control and Transmit PA control is via a 16 bit serial word, which is generated by the system controller. 15 bits of this serial word are used for the channel information, and 1 bit is used to setthe output power of the transmit PA. Theword length is sufficient to give full channel coverage over the range from 800 to 1000MHz with integer multiples of 50KHz. The section "system clock input" gives a detailed description. Not shown in the diagram are the voltage regulators for the receive LNA/first mixer, Transmit PA, TX mixer and the remainder of the circuit.There are 6 internal voltage regulators to ensure the minimum of mutual interference.
C C
8/16
STB4395
5 - POWER SUPPLIES 5.1 - Supplies The chip operates from a power supply of 3.0 to 5.5 Volts. All interface circuits to the baseband chips are operated between these supplies. Six on-chip regulators are included on-chip which provide to all parts of the circuit separate regulated voltage supplies of -2.85 0.15 Volts relative to the top rail for the RF circuitry, the IF circuitry, the digital circuitry and for the three VCO's. The chip can be operated in 3 modes, power down, receive and transmit. Power down is activated taking the Pin EN to VN . To transfer to the receive mode, NTXEN is taken to VP. The built-in regulators can be by-passed ,if so required. 5.2 - Ground Plane Connections The chip has been designed to be decoupled to the 6 - ELECTRICAL CHARACTERISTICS
Symbol VN VREG IRX ITX IQ Parameter Power Supply Voltage (unregulated) Power Supply bypassing Internal Regulators (this is also interface supply) Receive Mode Transmit Mode Standby/Power Down Min. -3 -2.7 Typ. Max. -5.5 -3 40 80 20 Unit V V mA mA A
positive supply, VP , at many points. Therefore it is strongly recommended that the chip be mounted on a board with a ground plane connected to VP. Because the base band chip is specified relative to a negative ground, it is further recommended that the board used is a 4 layer board with both a positive, VP , and negative ground plane VN . This has the additional advantage of providing good high frequency decoupling between supplies. The question as to whether to call VP or VN ground depends on which external equipment is connected. For testing the baseband section, this is VN ; for testing the radio chip, this is VP. In a product, this will depend on the application. For clarity all voltages specified in this document will be specified with respect to the supply, VP or VN , that the voltage normally tracks with when the supply is varied.
32 68
7 - TIMING INFORMATION 7.1 - Turn on-off Times Times are relative to the NTXEN transition (high to low for receive to transmit and low to high for transmit to receive).
Symbol tON tRAMPON tTXRX Parameter Turn-on Time From standby to receive PA Power Ramp up to reach -3dB of final power Switchover Time Transmit to Receive (LNA/first mixer active) Min. Typ. Max. 10 27.78 27.78 Unit s s s
7.2 - Channel Select Timing PRGCLK must be high before NPRGEN goes low to programme the synthesizer. Figure 2 : Timing of Serial Programming Data
Orde r of NPRGEN &PRGD unimportant NPRGEN PRGCLK
PRGD PROGRAM CODE Code changes on Rising Edge ofNPRGEN
4395-04.EPS
Note that although a new program code is implemented on the rising edge of the NPRGEN, the transmitted power level is delayed until at the start of the next burst of transmission. In order to change transmit power during a conversation, the required power code must be serially loaded with the power change instruction.
9/16
STB4395
8 - TRANSCEIVER SECTION
Symbol fOP Frequency Range Channel Frequency Accuracy Modulation Deviation (synchronised with72 Kbits/s data rate) POUTTX Output Power (300 balanced) high power mode Sensitivity (source 300 balanced) for 1E-3 BER Signal max. for 1E-3 BER 13 -103 -105 0 Description Min. 800 -1 0 18 Typ. Max. 1000 1 Unit MHz kHz kHz dBm dBm dBm
8.1 - Receiver-Input Specification
LNA, first mixer and buffer
Symbol Parameter Conversion voltage gain Available conversion power gain Input impedance Output impedance Source impedance Load impedance Noise figure 1dB compression point (input) Third order intercept (input) Min. Typ. 33.7 1.5 21.5 1.5 300 // 3pF 5k // 3pF 300 // -3pF 5k // -3pF 3.5 -24 -14 Max. Unit dB dB dB dBm dBm
First IF amplifier, second mixer and buffer
Symbol Parameter Conversion Voltage Gain Available Conversion Power Gain Input Impedance Output Impedance Source Impedance Load Impedance Noise Figure 1dB Compression Point (input) Third Order Intercept (input) Min. Typ. 22.0 1.5 16.3 1.5 700 // 2pF 2k // 2pF 700 // -2pF 2.8k // -2pF 6 -32 -22 Max. Units dB dB dB dBm dBm
Second IF amplifier
Symbol Parameter Conversion Voltage Gain Available Power Gain (to DISCO) Bandwith (3dB) Input Impedance Output Impedance (to DISCO) Source Impedance Load Impedance (at DISCO) Noise Figure 1dB Compression Point (input) Min. Typ. 82 3 86 3 3 10k // pF 1.1k // 2F 2.2k // -2pF see App. Diag. 6 -108 dB dBm Max. Unit dB dB MHz -
10/16
STB4395
8 - TRANSCEIVER SECTION (continued)
Dataslicer time constants
Symbol Slow Fast Hold Drift Rate 60mV < signal < 100mV Parameter Min. Typ. 3* 130* 1 Max. Unit ms s mV/ms
For 33nF capacitor at SLTC 8.2 - Transmitter-Output Specification
Symbol POUT LO Rejection Output Control Switch Parameter Output Power into 300 balanced, high power mode Min. 13 25 14 Typ. Max. Unit dBm dBC dB
TXFLT/NTXFLT output
Symbol Output Impedance Load Impedance (external) Voltage Out (channel frequency, application circuit of this D/S) Voltage Out (channel frequency-300.8MHz, app. cct of this D/S) Parameter Min. Typ. 2 1.2 200 80 Max. Units k k mVPP mVPP
8.3 - Synthesizer/Modulator/Channel Select Loop 8.3.1 - Synthesizer Phase Noise and Spurious Phase noise and spurious are measured at the RF outputs RF / NRF in transmit mode, no RF SAW filter.
Phase Noise (Average)
Offset Frequency from carrier 100kHz 500kHz 1MHz 10MHz Min. Typ. -106 -121 -127 -145 Max. Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Spurious
Offset Frequency from carrier 50kHz 100kHz 200kHz 200kHz to 10MHz 10MHz to 100MHz Min. Typ. -55 -63 -70 -75 -40 Max. Unit dBc dBc dBc dBc dBc
8.3.2 - Channel Select Loop
Symbol Frequency Frequency Steps Parameter Min. Typ. channel - 150.4 50 Max. Unit MHz kHz
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STB4395
8 - TRANSCEIVER SECTION (continued) 8.3.3 - Channel Frequency Setting 8.3.3.1 - General Case Using, from the divider ratios : and from the mixers : FCH = CH*FX/288 FIF2= FRX - FIF1 FRX = RX *FX/16 FIF1= FRF - FCH FIFT X = 0.5 *FTX FRF = FCH+FIFTX FTX = TX*FSYN/18 the RF frequency is related to the other frequencies by : = CH * FSYN/288 + TX * FSYN/18 * 0.5 FRF = FCH + FIFTX = FCH + FRX - FIF2 = CH * FSYN/288 + RX * FSYN/16 - FIF2 Hence the channel select input (15 of the 16 digits, see pin table, paragraph 1.4) serial data stream : CH = (FRF - TX*FSYN/18*0.5 ) * 288/FSYN = 288* F RF /FSYN - 3008 and CH = 288 (FRF + FIF2)/FSYN - 3042 where : FCH is the channel PLL synthesizer frequency FIF1 is the first if frequency (receive) FIF2 is the second if frequency (receive) FIFT X is the transmit if frequency FRF is the desired rf frequency FRX is the receive offset PLL frequency FSYN is the reference input frequency (on SYNCLK) FTX is the transmit offset PLL frequency RX is the fixed receive divide ratio of 169 TX is the fixed transmit divide ratio of 376 CH is the channel synthesizer divide ratio defined by the binary channel number, e.g. D14,D13,...........D0 The channel synthesizer provides integral division for all numbers between 3968 and 32764 (binary 000111110000000 to 111111111111100).Binary numbers outside this range will cause division ratios not directly related to binary code. 8.3.3.2 - Particular Case. with FSYN = 14.4MHz : FRX = 152.1MHz FTX = 300.8MHz FIFT X = 150.4MHz FIF1 = 150.4MHz FIF2 = 1.7MHz Then CH = 20 * FRF - 3008 Example : desired RF frequency, FRF = 866.05MHz Then substituting in : CH = 20*866.05-3008 = 14313 (binary 011011111101001)
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STB4395
8 - TRANSCEIVER SECTION (continued) 8.4 - System Clock Input
Symbol fREF (*1) VS IIH IIL Reference Frequency Input Voltage Swing, AC Coupled, referenced to VP Input Current-High (with respect to VN) Input Current-low (with respect to VN) 0.4 -40 40 Description Min. Typ. 14.4 0.8 Max. Unit MHz V A A
(*1) limits according to ETSI specification
8.5 - RF/NRF Receive/Transmit Pins
Symbol ZIN VSWR VIN DC Max. PIN AC Max. ZOUT VSWR DC Input Voltage AC Input Power Output Impedance (balanced, TX) 300 // 3pF Description Input Impedance (balanced, RX) Min. Typ. 300 // 3.5pF 1.5:1 0 0 Max. Unit V dBm -
8.6 - Digital Input Buffers NTXEN, PRGD, NPRGEN, PRGCLK, FN
Symbol VIH VIL IIH IIL Tt Upper Level Input Voltage Lower Level Input Voltage Input Current High Input Current Low Input Edge Transition 0.1 Description Min. VP -1 VN -0.4 -10 40 1 Typ. Max. VP +0.4 VN + 1 Unit V V A A s/V
8.7 - Digital Output Buffers xLOCK, DO
Symbol VOH VOL tR tF Description Upper Level Output Voltage Lower Level Output Voltage Rise Time (load of 5pF) Fall Time (load of 5pF) Min. VP -0.3 VN 0.3 0.4 Typ. Max. VP VN + 1 Unit V V s/V s/V
8.8 - Receiver - FSH Tri State Input
Symbol VIH VIL ITR IIH IIL Tt Description Upper Level Input Voltage Lower Level Input Voltage Tri State Current Input Current High Input Current Low Input Edge Transition 0.1 Min. VP -0.3 VN-0.4 -10 -100 100 1 Typ. Max. VP +0.4 VN + 1 10 Units V V A A A s/V
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STB4395
8 - TRANSCEIVER SECTION (continued) 8.9 - Receiver-RSSI Output The receiver output swings between VP and VN.The buffer output supplies a current to an on-chip resistor connected to VN . The output has to be smoothed externally with a capacitor to VN.
Symbol PMIN PMAX R OUT VMIN VMAX CF Description Min RF Input Power Registered Max RF Input Power Registered Output Resistance (internally connected to VN) Voltage for PMIN Voltage for PMAX conversion factor VN -44 50 VN+1.25 VN+0.25 -200 VN+2 Min. Typ. Max. -90 Unit dBm dBm k V V mV/decade
8.10 - Power Down Buffer, EN
Symbol VIH VIL IIH IIL tON tOFF Description Upper Level Input Voltage Lower Level Input Voltage Input Current High Input Current Low Buffer Delay to LOCK HI (1) Buffer Delay to min Supply Current (1) Min. VP -0.3 VN -0.4 -350 10 10 10 Typ. Max. VP +0.4 VN +0.3 Unit V V A A ms ms
(1) assumes application circuit with 100nF on each regulator.
8.11 - Transmitter-Data Inputs 8.11.1 - I,Q,REFIQ (STB4395A)
Symbol REXT R INT R IM VDC VDC match VS VS match Description External Input Resistance Internal Input Resistance RINT Matching Error DC Bias to REXT VDC Matching Error to REXT Peak Voltage Swing to REXT VS Matching Error to REXT Phase(I-Q) 88.5 90 0.45 0.5 0.96VHS Min. 6.5 32 Typ. 6.8 40 Max. 7 50 1 1.04VHS 5 0.56 0.5 91.5 Units k k % V mV V dB degrees
VHS = (VP + VN)/2 8.11.2 - I,Q,NI,NQ (STB4395) VHS = (VP+VN)/2 - VHR = (VP+VRD)/2
Symbol REXT R INT R IM VDC VDC match VS VS match Description External Input Resistance Internal Input Resistance RINT Matching Error DC bias to REXT VDC Matching Error to REXT Peak Voltage Swing to REXT VS Matching Error to REXT Phase (I/Ibar and Q/Qbar) Phase I to Ibar or Q to Qbar 88.5 90 0 0.7 0.75 VHS-0.7 32 Min. Typ. 2 40 50 1 VHR+0.7 12 0.85 20 91.5 Max. Unit k k % V mV V mV degrees degrees
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STB4395
9 - APPLICATIONS 9.1 - Typical DC connection schemes 9.1.1 - Internal Regulator The STB4395 has built-in internal regulators which allows 15mA to be used for external circuitry. The output of this regulator is -2.85V with respect to the positive supply rail. 9.1.2 - External Regulator The STB4395 will always generate its own supply voltage(-2.85V with respect to VP), but the I/O interfaces allow the STB4395 to swing its output levels to the supply rails (VP to VN ). The system and baseband controller can therefore be connected from the same -unregulated- supply and be individually regulated, if required . 9.2 - Application Circuits 9.2.1 - Introduction The STB4395 makes use of some unusual circuit Figure 3
5 0 SAW 8 66MHz L14 7 50 nH 3 00 700 and 2pF 700 and 2pF R18 5 L7 10 nH C26 56 0pF L8 8nH L10 8n H L11 10n H R21 0 -10k L16 2 70 nH R23 C24 0pF VP C3 10F NVBAT VRD NPRGE N PRGCLK R1 2k PRGD R2 2k NTXEN R4 2 k LOCK R7 2 k 5 R6 0 I R5 0 REFIQ R3 0 Q C2 0pF FN EN C11 SYNCLK DO FSH R12 50 RSSI L2 1 5n H R8 51 10n F C17 13 L3 1 5n H 100 nF C16 2-6p F 14 15 16 R13 5 .1k C15 82n F C19 8.2 nF 17 18 19 C20 3 3n F L6 8nH C27 0 pF C28 L9 68p F 8n H C40 5 6nF R19 27k C31 20 pF C46 VN 1 00 nF 20 21 22 23 24 25 26 27 28 29 30 31 32 35 34 33 C36 5. 6nF R24 5 .1k 36 10 0nF L17 47 nH C37 2-6p F L18 47 nH R25 100 C18 20 0nF 12 37 C38 C5 0p F C8 0pF C12 30 0p F C13 30 0p F C14 30 0p F R9 6.8 k 8 9 10 11 R10 6. 8k 7 42 R11 6. 8k 6 43 C34 44 C42 2 -50p F C45 82 0pF C48 4 7p F L23 10H 4 45 3 46 2 47 L1 330 H C1 56 pF C4 5 6pF C7 56p F C10 56 pF L4 56H 1 C6 1 00 nF C9 100 nF VN VN VN 64 63 62 61 60 59 58 57 56 55 54 VN 53 52 51 50 VN 49 48 VN L21 3 90 nH C22 10 0n F L5 8. 2nH L15 2 70 nH R16 4 .7k C29 1 00 nF L13 7 50 nH 20 SAW 15 0.4 MHz
configurations : - The STB4395operatesfrom positive ground. The decoupling of the supply lines should take into account that the a.c. ground connections will be reversed with respect to the baseband circuit and/or the microcontroller. The use of multilayer PCB is recommended. - The filters have been adapted for the best performance of the IC, although standard configurations are also considered. 9.2.2 - Fully Configured Applications Example Figure 3 is a typical application circuit for a complete system. It shows the typical external components to the circuit. As the reactance of the components is critical in many locations, the use of surface mounted componentsis essential. Atypical component list is also attached. It also shows the typical values for the the various VCO circuits.The values are very dependenton layout.
R15 2k
L19 12 00n H C43 1n F L20 3 90 nH
STB4395A
41
1 0n F C41 2-50 pF C33 39 38 C32
1k
C44 82 0pF
C49 4 7p F
TQFP 64 (from above)
40 1k 10n F 10n F
R26 10 k
L22 10H C47 100 nF
C21 4 7n F C16 , C15, C19, C21 , C23, C41, C45 provision for co nn ection to grou nd also
C25 10 0nF Approx value s of b uried trac k indu ctanc es to grou nd
L12 56H
C28 6 8p F
15/16
4395-05.EPS
R14 5 .1k
C23 4.7 pF
R17 2 0
R20 27k
R22 1 0k
C35 1 00p F
C39 2-50 pF
STB4395
PACKAGE MECHANICAL DATA 64 PINS - PLASTIC QUAD FLAT PACK (THIN)
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C L1
E
L
B
K
TF4 Q P6
Dimensions A A1 A2 B C D D1 D3 e E E1 E3 K L L1
Min. 0.05 1.35 0.18 0.12
Millimeters Typ.
1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00
Max. 1.60 0.15 1.45 0.28 0.20
Min. 0.002 0.053 0.007 0.0047
Inches Typ.
1 0o (Min.), 7o (Max.) 0.75 0.0157
0.055 0.009 0.0063 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0236 0.0393
Max. 0.063 0.006 0.057 0.011 0.0079
0.40
0.0295
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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TQFP64.TBL
PMTQFP64.EPS

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